1. Field of the Invention
The present invention relates generally to methods for fabricating thin film transistor (TFT) devices. More particularly, the present invention relates to methods for fabricating TFT devices with enhanced performance and enhanced alignment.
2. Description of the Related Art
Thin film transistor (TFT) devices are semiconductor devices typically formed employing a semiconductor channel layer and a pair of source/drain layers laminated over an insulator substrate rather than formed within a semiconductor substrate. TFT devices are extensively employed as switching devices and peripheral circuit devices within active matrix liquid crystal display (AMLCD) optoelectronic products. TFT devices are also employed as load transistors within synchronous dynamic random access memory (SDRAM) products.
While TFT devices are thus common in the microelectronic product fabrication art, thin film transistor devices are nonetheless not entirely without problems. In that regard, insofar as TFT devices are formed employing a semiconductor channel layer and a pair of source/drain layers laminated over an insulator substrate, rather than formed within a semiconductor substrate, TFT devices are thus often difficult to form with both enhanced performance and enhanced alignment.
It is thus desirable within the microelectronic product fabrication art to provide TFT devices, and methods for fabrication thereof, with enhanced performance and enhanced alignment.
It is towards the foregoing object that the present invention is directed.
Various TFT devices having desirable properties, and methods for fabrication thereof, have been disclosed within the microelectronic product fabrication art. Included but not limiting among such devices and methods are those disclosed within: (1) Lin et al., in U.S. Pat. No. 5,658,806 (a self-aligned planarizing method for forming a planar TFT device); and (2) Lee, in U.S. Pat. No. 5,937,283 (an additional self-aligned planarizing method for forming a trench TFT device).
Desirable within the microelectronic product fabrication art are additional TFT devices with enhanced performance and enhanced alignment, and methods for fabrication thereof.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a TFT device and a method for fabricating the TFT device.
A second object of the invention is to provide a TFT device and a method for fabricating the TFT device in accord with the first object of the invention, wherein the TFT device is fabricated with enhanced performance and enhanced alignment.
In accord with the objects of the invention, the invention provides a TFT device and a method for fabricating the TFT device.
In accord with the invention, the TFT device comprises a substrate. The TFT device also comprises at least one gate electrode formed over the substrate and separating a pair of source/drain layers also formed over the substrate. In addition, the at least one gate electrode is separated by a gate dielectric layer from a semiconductor channel layer also formed over the substrate and contacting the pair of source/drain layers. Within the TFT device, the pair of source/drain layers is formed of a silicon-germanium alloy material.
In accord with the invention, the method for fabricating the TFT device first provides a planar substrate. The method further provides for forming over the planar substrate a topographic first gate electrode and forming upon the topographic first gate electrode a first gate dielectric layer. In turn, the method provides for forming separated by the first gate electrode a pair of source/drain layers and forming contacting the pair of source/drain layers and the first gate dielectric layer a semiconductor channel layer. The method still further provides for forming contacting the semiconductor channel layer a second gate dielectric layer and forming contacting the second gate dielectric layer and also separating the pair source/drain layers a second gate electrode. Within the method: (1) the pair of source/drain layers is formed in a self aligned fashion with respect to the first gate electrode; and (2) the second gate electrode is formed in a self aligned fashion with respect to the pair of source/drain layers and the first gate electrode.
The invention provides a TFT device and a method for fabricating the TFT device, wherein the TFT device is fabricated with enhanced performance and enhanced alignment.
With respect to enhanced performance, the TFT device realizes that object by forming the TFT device with a pair of source/drain layers formed of a silicon-germanium alloy material.
With respect to enhanced alignment, the present invention realizes that object by forming the TFT device as a dual gate TFT device with: (1) a pair of source/drain layers formed in a self aligned fashion with respect to a first gate electrode; and (2) a second gate electrode formed in a self aligned fashion with respect to the pair of source/drain layers and the first gate electrode.